University of California, Riverside

Bourns College of Engineering

Walid A. Najjar

Faculty Profile

Faculty Profile

Walid A. Najjar

Professor of Computer Science and Engineering
Walid A. Najjar

Ph.D. Computer Engineering
University of Southern California, 1988

421 Winston Chung Hall
University of California, Riverside
Riverside, CA 92521

Telephone: 951-827-4406
Facsimile: 951-827-4643
Personal Webpage

Former Institution: Colorado State University


  • PhD Computer Engineering 1988 University of Southern California
  • M.S. Computer Engineering 1985 University of Southern California
  • B.E Electrical Engineering 1979 American University, Beirut Lebanon


  • 1995 - 1996 Graduate Teaching Award, College of Natural Sciences, Colorado State University
  • 2007 Fellow, IEEE
  • 2009 Fellow, AAAS

Research Areas

Dr. Najjar's main field of research is the design of computer systems in general with emphasis on parallel, reconfigurable and custom-designed systems. His main research effort has been on the interface between hardware and software including the interactions and performance implications for the system design. Dr. Najjar is leading a major research effort in the area of FPGA-based code acceleration. More information on the Riverside Optimizing Compiler for Configurable Computing (ROCCC) can be found at

Selected Publications

  • J. Villarreal, A. Park, W. Najjar and R. Halstead. Designing Modular Hardware Accelerators in C With ROCCC 2.0, in The 18th An. Int. IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM), Charlotte, NC, May 2010.
  • R. Moussalli, M. Salloum, W. Najjar and V. Tsotras. Accelerating XML Query Matching Through Custom Stack Generation on FPGAs, Proc. Int. Conf. on High-Performance Embedded Architectures and Compilers, January 25-27, 2010, Pisa, Italy.
  • W. Najjar and J. Villarreal. Modular Design of FPGA-Based Accelerators in C, Military and Aerospace Programmable Logic Devices (MAPLD), NASA Goddard Space Flight Center, Greenbelt, MD, August 2009.
  • W. Najjar and J. Villareal. Reconfigurable Computing in the New Age of Parallelism. SAMOS Workshop, July 2009.
  • D. C. Suresh, B. Agrawal, W. Najjar and J. Yang. Tunable and Energy Efficient Bus-Encoding Techniques, in IEEE Trans. on Computers, Vol. 58, No. 8, August 2009.
  • A. Mitra, M. Vieira, P. Balakov, V. Tsotras and W. Najjar. Boosting XML Filtering Through A Scalable FPGA-based Architecture, in Fourth Biennial Conference on Innovative Data Research, Asilomar, CA, January 2009.
  • D. C. Suresh, B. Agrawal, J. Yang, and W. Najjar. Energy-efficient encoding techniques for off-chip data buses. ACM Trans. Embedd. Comput. Syst. 8, 2, Article 9 (January 2009), 23 pages.

More Information 

General Campus Information

University of California, Riverside
900 University Ave.
Riverside, CA 92521
Tel: (951) 827-1012

College Information

Bourns College of Engineering
446 Winston Chung Hall

Tel: (951) 827-5190
Fax: (951) 827-3188